This invention relates to the manufacture of transistors incorporating ferroelectric thin films therein, and specifically to fabrication of a metal/ferro metal oxide semiconductor (MFMOS) and metal/ferro metal semiconductor (MFMS) transistors using a nitride replacement technique.
Ferroelectric thin films are used in nonvolatile memories. Metal-ferroelectric-metal-silicon semi-conductors, also referred to herein as ferroelectric memory (FEM) cells are particularly useful as memory transistors. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a nondestructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators in silicon (MFIS) FET, metal ferroelectric metal semiconductor (MFMS) FET, and metal ferroelectric metal oxide semiconductor (MFMOS) FET.
It is critically important that, during etching of the gate stack of MFMOS and MFMS memory transistors, the etching does not extend significantly into the silicon. The thickness of the gate oxide of a MFMOS memory transistor is very thin, and it is exceptionally difficult to stop the gate stack etching process at the level of the gate oxide. Large source/drain series resistances may occurs if excessive amounts of silicon are consumed by the gate stack etching process. In the case of MFMS memory transistors, the surface channel is very shallow. This channel may be completely removed by etching during the gate stack etching process if proper controls are not maintained.
A method of fabricating a ferroelectric memory transistor includes preparing a substrate, including isolating an active region; forming a gate region; depositing an electrode plug in the gate region, depositing an oxide side wall about the electrode plug; implanting Arsenic ions to form a source region and a drain region; annealing the structure to diffuse the implanted ions; depositing an intermediate oxide layer over the structure; removing the electrode plug; depositing a bottom electrode in place of the electrode plug; depositing a ferroelectric layer over the bottom electrode; depositing a top electrode over the ferroelectric layer; depositing a protective layer; depositing a passivation oxide layer over the structure, and metallizing the structure.
It is an object of the invention to provide a method of fabricating MFMOS memory transistors and MFMS memory transistors which does not require exceptionally precise etching procedures.
Another object of the invention to provide a method of fabricating MFMOS memory transistors and MFMS memory transistors which will reduce fabrication cost and increase production output.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.